Curriculum Vitae

name Bernd Paysan my photo
date of birth 1970/03/03
nationality German

Education

1976-1978 Primary School [html]Neubiberg near Munich
1978-1980 Primary School [html]Samberger Schule in Munich
1980-1989 Abitur [html]Gymnasium in Pullach/Munich
1990-1997 Diplom Computer Science at [html]TU München

Alternative Civilian Service

1989-1990 alternative civilian service in [php]Martha-Maria hospital in Munich

Employment History

Date Employer & Role
2010/2-2011/9 [html]Dialog aquired power management design team
Senior Design Engineer:
  • Gasgauge: Firmware development: rewrote smart battery firmware algorithm to b16. Adapted algorithm for battery aging.
    Concept for fast battery characterization.
    Software: Debugger GUI and demonstration/data logging GUI, characterization data evaluation, validation tools.
    Digital design: integration into test chip.
2008/7-2010/2 [html]Diodes aquired Zetex PLC
IC Design Engineer:
  • Gasgauge: Digital design: Integration of b16 CPU, I²C interface, RAM, ROM, SPI for debugging, work on 10 bit ADC, debugger interface for software development and demonstration GUI (1 year)
  • Charger: Intersil 9221/Maxim 8601 clone, analog design: Comparator blocks, power transistors (including layout and device engineering), architecture, and voltage mode regulator (1 year)

Administration of the Munich Linux network
2005/4-2008/7 Zetex aquired Mikron AG
IC Design Engineer:
  • Direct digital feedback amplifier ([html]DDFA): Project leader of the modulator part. Digital design of I²S input, equalizer DSP, upsampling DSP, volume control; conversion from FPGA tool-based output stage. Implementation of a GUI to operate the device and design filters (3 years).

Administration of the Munich Linux network
1998/10-2005/4 Mikron AG
IC Design Engineer:
  • Smart Battery Fuel Gauge, third generation: Developed software simulator to develop and debug firmware, participated in firmware development, debugging and prototype evaluation (1 year)
  • Smart Battery Charger: Software simulator and firmware development, participated in SMBus interface development (half a year), redesign of digital part (new timer and watchdog, debugged SMBus) for second release (1/2 year)
  • Smart Battery Fuel Gauge, fourth generation: Software simulator, technical project leader. Integration and debugging of digital part, evaluation and test development (1.5 years).
  • Acoustic Touch Screen Controller (IntelliTouch): Project leader, digital design (integration of Inventra USB and 8051, flash and SRAM), specification, analog supervision (analog part comprises two PLLs, amplification, bandpass filter, pipelined ADC) (2 years).
  • Laser barcode reader: Project leader, digital design (integration of b16, RAM, ROM, and SPI interface) (2 years, continued at Zetex)

From 2005 also administration of the Unix/Linux network
1997/7-1998/10 [html]Mixed Mode ASIC Design
ASIC Designer: consulting customers in ASIC projects. Wrote a C++ Model for a CAN peripheral for Siemens HL. Wrote tests for the VHDL model of the CAN peripheral.
Designed a generic peripheral class, support for event driven C++ hardware simulation library.
1990/1-now Own company
Software engineer: development of Forth systems, Forth GUIs, part-time job, see projects below

Knowledge

Languages

German (mother tong), English (excellent), French (fluent), Chinese (moderate, 2.5 years course, experience during travels and with coworkers)

Computer Languages

C, C++, Verilog, VHDL, Forth, 68k assembler, x86 assembler, PIC17 assembler, Lisp/Scheme, Modula-II, Java, Prolog, (La)TeX, HTML, TCL, bash, Matlab/Simulink

OS (System Programming)

Linux, Windows, (also, but dated: DOS, Atari TOS, HP-UX)

Tools

network server apache, squid, dokuwiki, postfix, dovecot (and more)
RTL synthesis RTL Compiler, Ambit, Design Compiler, Leonardo, Quartus
Simulation NC Sim, Modelsim, Affirma, Spectre, Ultrasim, Hsim, Eldo
Analysis Leda, Formality, Primetime
Design Environment Cadence 5.x, Mentor Graphics
Layout editor Cadence Virtuoso & Encounter, Mentor tools

Development environments

Emacs/Makefiles, MS VC++; Version control systems: bzr, subversion, cvs

Projects

Date Project
2002, 2004 b16 scalable minimalistic CPU; USB core, see [html]http://bernd-paysan.de/b16.html
1997-now Development of a GUI editor and a underlying widget library for bigFORTH. bigFORTH port to Linux and Windows, licence change to GPL. About 100 widget classes. Published in Tagungsband Forth Tagung '97, Bernd Paysan, "MINOS - Visual bigFORTH", published on EuroForth'97, find the paper in [html]http://bernd-paysan.de/bigforth.html
1994-1997 Design and implementation of a stack-based VLIW processor architecture especially suited for signal processing, while having low-latency calls and branches to fit high level language demands. Specifying the instruction set architecture, development of a simulator and demo programs, implementation in 12k lines synthesizable Verilog, performance estimation in 0.35u CMOS: at 300 MHz around 2 GOPS. Implements functional units, FPU, caches, instruction decoding, branch unit, bus interface...
Started to write a compiler prototype (not finished).
Diploma Thesis "Implementation of the 4stack processor using Verilog", [html]http://bernd-paysan.de/4stack.html
1992-now Development of a portable free Forth system based on a C-coded engine (GNU Forth, Gforth), written with a loosely-knit team over the internet. Published e.g. in EuroFORTH '93 conference proceedings, M. Anton Ertl, "A portable Forth engine", see also [html]http://bernd-paysan.de/gforth.html
1991-1994 Porting bigFORTH to 386/DOS, other features as above, object oriented extension, text-based GUI library.
1988-1991 Development of a Forth compiler system (bigFORTH) on a 68k platform (Atari ST). Generation of peephole-optimizied code. Integrated development environment, featuring decompiler, debugger, assembler, disassembler, support of host OS GUI. Published in VD 3/1991, Bernd Paysan, "Ein optimierender Forth-Compiler" Runs standalone on a 68k VME box, too.

US Patents

Pat. No. Title
6,125,381 Recursively partitioned carry select adder
5,918,075 Access network for addressing subwords in memory for both little and big endian byte order

Hobbies

Sports Cycling, hiking, snorkling, nordic skiing
Books Fantasy like [html]Terry Pratchett, Harry Potter, [htm]Journey to the West
Traveling Great landscape, e.g. in east Asia
Art Painting, photographing, writing satires

Look here for more details [html]http://bernd-paysan.de/hobby.html

Club Activities

Opportunity

My main interest goes to the digital side of mixed-signal design, especially in connection with signal processing, with emphasis on a hardware-software codesign. I can think for myself, and as a consequence come up with new and different solutions. Cost and time to market are as important for me as technical excellence. Work on intellectually rewarding projects is an important motivation for me as are trust and responsibility. I see teamwork not just as dividing work up between people, but as room for open discussion, being a consultant and consulting others when necessary.


Created 30dec1997. Last modified: 10aug2011 by MailBernd PaysanPGP key