The market place consideration shows that the 4stack processor would ideally go into appliances with high DSP performance requirements. The integration of chips used in this field has gone so far, that processors aren't sold as separate chips, but as cores. Low power consumption and low area are key requirements for this market, compatibility with desktop or workstation processors is not required.
There is no successful player on the market for combined integer and DSP processing cores; ARM is market leader for integer oriented cores, TI is market leader for DSPs.
The plan therefore is to license the 4stack processor core as IP.
The first step is to realize the 4stack processor in a FPGA. This allows to fix bugs in the Verilog code, and provides software developer (for compiler and operating systems) with a prototype. FPGAs and the respective development tools are also cheap enough to start without external capital. This prototype allows to demonstrate that the concept works, and allows potential customers to examine if it fits their needs.
estimated development time [months]: 3
The next step - probably together with a pilot customer - is then to port the 4stack processor to a standard state of the art process, e.g. TSMC's .18u process.
estimated development time [months]: 6-12